The channel length of the dynamic random access memory (DRAM) transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device.
The present processing of DRAM structures in an array uses nitride spacers in a gate stack to provide margin for the borderless contacts. These same spacers in the support devices increase the distance of the P-FET extension and halo implants from gate polysilicon.
The top of the gate stack is more severely exposed to the borderless contact etch. Therefore, for improved borderless contact margin it is preferable to have a thicker borderless contact barrier at the top compared to the bottom. Divakaruni et al., U.S. patent application Ser. No. 09/325,942, filed Jun. 4, 1999 entitled "Modified Gate Conductor Processing for Poly Length Control In High Density DRAMs" describes a stack formed with tungsten silicide enclosed by nitride spacers before sidewall oxidation. The presence of these spacers ameliorates the need for additional large spacers in the array for borderless contact margin. However, the support P-FETs still need an offset from the support N-FETs for the extension and the halo implants. This offset currently is about 30 nm and the use of nitride spacers in the array at these dimensions uses up valuable space between the tightly packed gates and causes severe constraints for void free gapfill at low temperatures.
The present invention is directed to overcoming the problems discussed above in a novel and simple manner.